Multi-orientation integrated cell, in particular input/output cell of an integrated circuit

ABSTRACT

An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/865,618, filed on Sep. 25, 2015, and entitled “Multi-OrientationIntegrated Cell, In Particular Input/Output Cell of an IntegratedCircuit,” which application claims the benefit of French PatentApplication No. 1460877, filed on Nov. 12, 2014, which applications arehereby incorporated herein by reference.

TECHNICAL FIELD

Embodiments of the invention relate to integrated circuits, and moreparticularly cells of such a circuit. For example, input/output cellsthat are able to take various orientations on the integrated circuit asa function of their location and containing components, for example, butnot limited to, thin gate oxide MOS transistors.

BACKGROUND

In 28 nanometer (nm) CMOS technologies and above, the orientation of thegates of the transistors on the semiconducting substrate in severaldirections is possible, in particular in a vertical direction or in ahorizontal direction.

On the other hand, in CMOS technologies below 28 nm, the orientation ofcertain components on the substrate may become critical since suchcomponents may, for example, be used only in a single direction. This isthe case for example with thin gate oxide MOS transistors typicallyhaving an oxide thickness of less than or equal to 2 nm. Typically, suchtransistors have a vertical gate orientation on the substrate, that isto say perpendicular to an oblique direction of implantation performedin a direction of implantation in such a way as to form doped source anddrain zones (commonly designated by the person skilled in the art by theterm “Halo” or “pocket”) under the gate of these transistors.

Indeed, lithography and technology constraints may prohibit the use ofsuch transistors in a horizontal direction. Other components remainmulti-orientation however. This is the case, for example, with thickgate oxide MOS transistors, typically having a gate oxide thickness ofgreater than or equal to 3 nm with sufficient gate dimensions measuredlength-wise along the channel (drain—source distance) of, for example,greater than or equal to 150 nm.

However, in an integrated circuit, certain cells may be disposedaccording to different orientations as a function of their location onthe integrated circuit.

This is the case, for example, with the input/output cells which aregenerally disposed within a rectangular annulus around the core of theintegrated circuit.

Also, typically, as a function of the location of an input/output cellin another branch of the rectangular annulus, certain components, suchas, for example thin gate oxide MOS transistors, may then exhibit avertical orientation or else a horizontal orientation. The transistorsexhibiting a horizontal orientation typically must consequently undergoa rotation to again exhibit a vertical gate orientation.

Hence, an approach includes developing, for these advanced technologies,two libraries of cells containing orientation-sensitive components.

Also, the cells of the first library are, for example, intended to beplaced in a horizontal branch of the input/output cell annulus so thatthe thin gate oxide transistors, for example, are vertically oriented.

The homologous cells of the other library are then intended to bedisposed in a vertical branch of the annulus so that once again the thingate oxide transistors exhibit a vertical gate orientation.

That said, not only does such an approach require the development andthe qualification of two libraries of cells, but furthermore thedesigner typically must each time analyze the location of the cell onthe integrated circuit so as to extract the corresponding cell from oneor the other of the libraries, with the potential risk of errors.

SUMMARY

According to one embodiment, it is proposed, for cells comprisingorientation-sensitive components, to develop only a single library ofcells that are capable of being disposed at any site of the integratedcircuit, for example, of an annulus of input/output cells, while on eachoccasion providing that the orientation-sensitive components, forexample thin gate oxide transistors, having a correct orientation areactually electrically functional.

According to one aspect, there is proposed an integrated circuitcomprising at least one integrated cell, for example an input/outputcell, disposed at a location of the integrated circuit, for example, ina branch of a rectangular annulus of input/output cells. That said, suchan integrated cell may also be a so-called “cluster” input/output cellaccording to terminology used by the person skilled in the art, that isto say placed directly at a location of the core of the integratedcircuit with any a priori orientation.

The at least one integrated cell comprises two first integrated devices,for example, thin gate oxide MOS transistors, connected to at least onesite of the cell by way of a multiplexer and respectively oriented intwo different directions of orientation, only the first device orientedin one of these directions of orientation being usable.

The cell moreover comprises a controller configured so as to detect thatone of the directions of orientation which, having regard to thedirection of the cell at the location, allows the corresponding firstdevice to be usable, and so as to control the multiplexer in such a wayas to actually connect the first usable device electrically to the atleast one site.

A usable device is in particular a device exhibiting a normal, that isto say non-degraded, operating state.

According to one embodiment, the controller includes a detection circuitcomprising two integrated test devices respectively oriented in the twodirections of orientation, each test device comprising an elementexhibiting a different characteristic according to the direction oforientation and representative of the usable or non-usable character ofa first device. This element may be, for example, a doped zonepossessing a part extending under the gate of the transistor, thecharacteristic then being the dimension of the part measured length-wisealong the channel, or else the element can be the gate of a testtransistor, the characteristic then being the roughness of the gate. Adetector may be configured to analyze the characteristics of theelements of the two test devices and deliver a control signal for themultiplexer.

In practice, according to an embodiment, the detector is advantageouslyconfigured to analyze the characteristics of the elements on the basisof an electrical parameter of the test devices, for example, thethreshold voltage or the leakage current of a transistor.

According to another embodiment, the two integrated test devices aredifferent from a first device and usable in the two directions oforientation. These two test devices can thus be thick gate oxidetransistors.

According to another possible embodiment of the invention, the twointegrated test devices are analogous to a first device. Statedotherwise, the two integrated test devices can also be, for example,thin gate oxide transistors.

The two directions of orientation are for example orthogonal, typicallyvertical and horizontal.

According to another embodiment, each first device is a thin gate oxideMOS transistor, with the longitudinal direction of the gate, that is tosay the direction perpendicular to the length of the channel, definingthe direction of orientation of the MOS transistor.

According to another embodiment, each test device is a thick gate oxideMOS transistor, with the longitudinal direction of the gate defining thedirection of orientation of the MOS transistor. The element is a dopedzone possessing a part extending under the gate of the transistor, withthe characteristic being the dimension of the part measured in thedirection of the length of the channel.

The electrical parameter is then advantageously the threshold voltage ofeach test transistor, and the detector is advantageously configured todetect that one of the test transistors, which exhibits the highestthreshold voltage, and to deliver to the multiplexer a control signalselecting the thin gate oxide MOS transistor having the same directionof orientation as that of the test transistor exhibiting the highestthreshold voltage.

According to another embodiment, each integrated test device is a firstdevice and the element is then, for example, the gate of the testtransistor, with the characteristic being the roughness of this gate.

The electrical parameter is then advantageously the leakage current ofeach test transistor, and the detector is configured to detect one ofthe test transistors which exhibits the smallest leakage current, and todeliver to the multiplexer a control signal selecting the thin gateoxide MOS transistor having the same direction of orientation as that ofthe test transistor exhibiting the smallest leakage current.

According to another embodiment, the integrated circuit can also includea rectangular annulus comprising several integrated cells forminginput/output cells of the integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and characteristics of the invention will be apparenton examining the detailed description of wholly non-limiting embodimentsand the appended drawings, in which:

FIG. 1 is a block diagram of an integrated cell according to anembodiment of the invention;

FIG. 2 is a block diagram of a controller of the integrated circuit;

FIG. 3 is a schematic of a thin gate oxide MOS transistor;

FIG. 4 is a schematic transverse sectional view along the line IV-IV ofFIG. 3;

FIG. 5 is a schematic of a thin gate oxide MOS transistor;

FIG. 6 is a schematic transverse sectional view along the line VI-VI ofFIG. 5;

FIG. 7 is a schematic of a multi-orientated thick gate oxide MOStransistor;

FIG. 8 is a schematic transverse sectional view along the line VIII-VIIIof FIG. 7;

FIG. 9 is a schematic of a multi-orientation thick gate oxide MOStransistor;

FIG. 10 is a schematic transverse sectional view along the line X-X ofFIG. 9;

FIG. 11 is a schematic of the controller;

FIG. 12 is a schematic of a comparator of the controller of FIG. 11;

FIGS. 13 and 14 are schematics of test devices of the controller; and

FIG. 15 is a block diagram of an integrated circuit having a rectangularannulus.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In FIG. 1, the reference CEL designates an integrated cell disposed at alocation EMP of an integrated circuit IC. This cell CEL is, for example,an input/output cell although this example is not limiting.

The cell CEL comprises two first integrated devices DV1, DV2, forexample thin gate oxide MOS transistors having an oxide thickness ofless than or equal to 2 nm.

The first device DV1 is oriented in the direction Di while the firstdevice DV2 is oriented in the direction D2. These two directions areorthogonal.

Each device is supplied between a supply voltage Vdd and ground GND.

When the device DV1 or DV2 is a thin gate oxide MOS transistor, theorientation D1 or D2 corresponds to the orientation of the gate, that isto say its longitudinal direction, that is to say its direction measuredperpendicularly to the length of the channel (drain—source distance).

The two first devices DV1 and DV2 are connected to a site A of the cellCEL by way of a multiplexer MUX controlled by a control signal SELwhich, as a function of the logic state 1 or 0, will control themultiplexer MUX in such a way that the input E1 is actually connectedelectrically to the site A or that the input E2 is actually connectedelectrically to the site A.

The control signal SEL is delivered by a controller 1, which isconfigured to detect those of the directions of orientation D1 or D2which, having regard to the disposition of the cell at the location EMP,allows the corresponding first device DV1 or DV2 to be usable.

Of course, as illustrated by a dashed line in FIG. 1, the cell CEL maycomprise other integrated devices such as, for example, devices DV3 andDV4, which may be multi-orientation devices, that is to say notsensitive to a particular direction of orientation. By way ofindication, these devices DV3 and DV4 can comprise thick gate oxide MOStransistors, having an oxide thickness of typically greater than orequal to 3 nm and having gate lengths (dimensions measured in thechannel direction) of typically greater than or equal to 150 nm, forexample equal to 150 nm.

In FIG. 2, it is seen that the controller 1 comprises a detectioncircuit 10 comprising two integrated test devices DVT1 and DVT2respectively oriented in the two directions of orientation D1 and D2.

As will be seen in greater detail hereinafter, each test devicecomprises an element exhibiting a different characteristic according tothe direction of orientation and representative of the usable ornon-usable character of a first device (for example a thin gate oxideMOS transistor).

The controller 1 also comprises a detector ii configured to analyze thecharacteristics of the elements of the two test devices DVT1 and DVT2and deliver the control signal SEL for the multiplexer so as to selectthat one of the two first devices DV1 and DV2 which will be usablehaving regard to the disposition of the cell at the location EMP.

In practice, as will be seen in greater detail hereinafter, the detector11 is configured to analyze the characteristics of the elements on thebasis of an electrical parameter of the test devices DVT1 and DVT2.

In FIG. 3 and in FIG. 4, which is a transverse section along the lineIV-IV of FIG. 3, the device DV1 is a thin gate oxide MOS transistor.

Likewise, as illustrated in FIG. 5 and in FIG. 6, which is a transversesection along the line VI-VI of FIG. 5, the device DV2 is also a thingate oxide MOS transistor.

As illustrated in FIG. 3, the transistor DV1 comprises above an activezone made in a semiconducting substrate 3, a gate GR, for example apoly-silicon line, electrically insulated from the active zone by a gateoxide, and oriented in the longitudinal direction DRL, which correspondsto a direction of orientation DOK, typically a vertical direction, forwhich the transistor is usable, that is to say exhibiting normaloperation.

Indeed, as illustrated in FIG. 3, a conventional step of fabricating athin oxide transistor such as this comprises a dual oblique implantation30 of dopants in a direction of implantation DI, doing so in both sensesof this direction so as to form, as illustrated in FIG. 4, source anddrain zones comprising parts 31 and 32 extending under the gate GR inthe transverse direction DRT. These zones 31 and 32 are commonlydesignated by the person skilled in the art by the name “Halo” or“pocket”.

These zones 31 and 32 have a dimension DM, measured in the transversedirection DRT, and define the length LC of the channel of thetransistor.

In FIG. 5, the device DV2 is oriented in the direction DRL, which ishere a horizontal direction and which is considered to be a direction oforientation DNOK leading to a device DV2, which is unusable since itexhibits degraded operation with respect to the normal operation of thedevice.

Indeed, as seen in FIG. 5, the direction of orientation DRL or DNOK ofthe device DV2 is parallel to the direction of implantation DI.

This therefore results, as illustrated in FIG. 6, in zones 31 and 32exhibiting a very small, or indeed zero, dimension DM, which is in anyevent much less than the dimension DM of a transistor of FIG. 4.

Whereas in FIGS. 2 to 6, the direction of orientation Di is consideredto be the direction DOK, that is to say that leading to a usablecharacter of the thin gate oxide transistor and that the direction D2 isconsidered to be the direction DNOK leading to an unusable transistorsince it exhibits degraded operation, the direction Di could be as afunction of the location of the cell within the integrated circuit andits disposition, the direction DNOK and the direction D2 the directionDOK.

In FIG. 7 and FIG. 8, which is a transverse section along the lineVIII-VIII of FIG. 7, the integrated test device DVT1 is amulti-orientation thick gate oxide MOS transistor.

Likewise, as illustrated in FIG. 9 and in FIG. 10 which is a transversesection along the line X-X of FIG. 9, the test device DVT2 is also amulti-orientation thick gate oxide MOS transistor.

In general, the methods for fabricating a thick gate oxide transistorprovide for an implantation tilted in two orthogonal directions and inboth senses for each direction.

Stated otherwise, East-West-South and North implantations of dopants areundertaken for these thick gate oxide transistors in such a way as toproduce the so-called “Halo” or “pocket” zones.

That said, when thick gate oxide transistors such as these are used astest transistors, the oblique implantation in the two orthogonaldirections is replaced, by a dual oblique implantation analogous to thatperformed for producing the thin gate oxide transistors and performed inthe direction of implantation DI.

Thus, as illustrated in FIG. 8, when the test transistor DVT1 isoriented in the direction Di perpendicular to the direction ofimplantation D1, we obtain the zones 31 and 32 extending amply under thegate GR and having dimensions DM1 measured in the sense of thetransverse direction DRT.

Such a test transistor DVT1 then exhibits a threshold voltage Vt1.

On the other hand, as illustrated in FIG. 9, when the dual implantation30 is undertaken in the direction of implantation DI on the transistorDVT2 oriented in the direction D2, we obtain, as illustrated in FIG. 10,zones 31 and 32 having a very small, or indeed zero, dimension DM2,which is in any event less than the dimension DM1.

The threshold voltage Vt2 of the transistor DVT2 is then less than thethreshold voltage Vt1 of the test transistor DVT1.

The detector 11 will then use this electrical parameter (thresholdvoltage) to determine which of the devices DV1 and DV2 is oriented inthe appropriate direction DOK and control the multiplexer accordingly.

More precisely, as illustrated in FIG. 11, the detection circuit 10comprises the two test transistors DVT1 and DVT2 connected between thesupply voltage Vdd and ground GND, the gate and the drain of eachtransistor DVT1 being linked to the voltage Vdd while the source islinked to ground GND by way of the resistors R1 and R2.

The sources of the two transistors are linked to the +and − inputs of acomparator 11 whose output OUT delivers the signal SEL.

By way of nonlimiting example, the comparator 11 is, as illustrated inFIG. 12, based on an operational amplifier with differential structurewith two stages having a bias voltage Vbias.

Thus, if the threshold voltage Vt2 of the transistor DVT2 is greaterthan the threshold voltage Vt1 of the transistor DVT1, then the outputvoltage of the comparator will be in the high state leading to the 1logic state of the signal SEL.

If on the other hand the threshold voltage Vt1 of the test transistorDVT1 is greater than the test voltage Vt2 of the test transistor DVT2,then the output voltage of the comparator 11 will be in the low stateleading to a o logic level of the signal SEL.

Whereas in the embodiment which has just been described, the testdevices were transistors different from the transistors DV1 and DV2,that is to say different from the thin gate oxide transistors, it ispossible, as illustrated in FIGS. 13 and 14, to also use thin gate oxidetransistors as test transistors DVT1 and DVT2.

More precisely, the first test transistor DVT1 will be oriented in thedirection Di, which is assumed here to be the direction DOKcorresponding to a usable character of a thin gate oxide transistor.Such a transistor exhibits a leakage current Id_(off1).

For its part, the test transistor DVT2 is oriented in the direction D2,which is assumed here to be the direction DNOK leading to an unusablecharacter of a thin gate oxide transistor. Indeed, in this case, thelithography constraints lead to a gate GR exhibiting a greater roughnessthan the roughness of the gate GR of the transistor DVT1.

This consequently results in a greater leakage current I_(off2) of thetransistor DVT2 than the leakage current Id_(off1) of the transistorDVT1.

This time it is this electrical parameter, which will be used by thedetector 11 to determine that one of the two transistors DV1 and DV2which is oriented in the appropriate orientation.

In practice, it will be possible to use a diagram analogous to thatillustrated in FIGS. 11 and 12 with the gate and the source of each testtransistor DVT1 and DVT2 linked to ground and the drain linked to thesupply voltage Vdd by way of the resistors R1 and R2.

FIG. 15 illustrates a rectangular annulus RG comprising a plurality ofintegrated cells CEL of the type of those which have just beendescribed. The rectangular annulus RG surrounds the core CR of theintegrated circuit IC.

Also it is seen that according to the location EMP1 or EMP2 of a cellCEL1 or CEL2, the correct direction of orientation for the thin gateoxide transistors will not be the same. Thus, if the direction D1 is,for example, the direction DOK for the cell CEL1, this direction D1 willthen be the direction DNOK for the cell CEL2. On the other hand, thistime it is the direction D2, which will be the direction DNOK for thecell CEL2, whereas it was not for the cell CEL1.

What is claimed is:
 1. An integrated circuit, comprising: a multiplexercoupled to a site of an integrated cell disposed at a location of anintegrated circuit; a first thin gate oxide transistor configured toexhibit normal operation in a first direction of orientation anddegraded operation in a second direction of orientation, the first thingate oxide transistor having a terminal coupled to a first inputterminal of the multiplexer; a second thin gate oxide transistorconfigured to exhibit normal operation in the second direction oforientation and degraded operation in the first direction oforientation, the second thin gate oxide transistor having a terminalcoupled to a second input terminal of the multiplexer; and a controllerconfigured to detect a usability of the first thin gate oxide transistorand the second thin gate oxide transistor based on an electricalcharacteristic indicative of the first direction of orientation or thesecond direction of orientation, the controller being further configuredto control the multiplexer to couple the terminal of the first thin gateoxide transistor or the terminal of the second thin gate oxidetransistor to the site.
 2. The integrated circuit of claim 1, wherein anoxide thickness of at least one of the first thin gate oxide transistoror the second thin gate oxide transistor is less than or equal to about2 nanometers.
 3. The integrated circuit of claim 1, wherein thecontroller comprises a detection circuit having two integrated testdevices separate from the first thin gate oxide transistor and thesecond thin gate oxide transistor, a first one of the two integratedtest devices being oriented in the first direction of orientation, asecond one of the two integrated test devices being oriented in thesecond direction of orientation, the two integrated test devices beingusable in each of the first direction of orientation and the seconddirection of orientation.
 4. The integrated circuit of claim 3, whereineach of the two integrated test devices comprises an element exhibitingthe electrical characteristic according to first direction oforientation and the second direction of orientation and representativeof the normal operation or the degraded operation of the first thin gateoxide transistor and the second thin gate oxide transistor.
 5. Theintegrated circuit of claim 4, wherein the controller further comprisesa detector configured to analyze the electrical characteristic of theelement of each of the two integrated test devices and to deliver acontrol signal to the multiplexer.
 6. The integrated circuit of claim 4,wherein the electrical characteristic comprises a threshold voltage ofeach of the two integrated test devices.
 7. The integrated circuit ofclaim 3, wherein each of the two integrated test devices comprises athick gate oxide transistor, a longitudinal direction of each gatedefining a direction of orientation of the thick gate oxide transistor.8. The integrated circuit of claim 7, wherein an oxide thickness of thethick gate oxide transistor is greater than or equal to about 3nanometers.
 9. The integrated circuit of claim 7, wherein a gate lengthof the thick gate oxide transistor is greater than or equal to about 150nanometers.
 10. A method of operating an integrated circuit, the methodcomprising: detecting, by a controller, a usability of a firstintegrated device and a second integrated device based on an electricalcharacteristic indicative of a first direction of orientation or asecond direction of orientation, the first integrated device exhibitingnormal operation in the first direction of orientation and degradedoperation in the second direction of orientation, the second integrateddevice exhibiting degraded operation in the first direction oforientation and normal operation in the second direction of orientation;sending, by the controller, a control signal to a multiplexer based onthe usability of the first integrated device and the second integrateddevice detected by the controller; and coupling, by the multiplexer andbased on the control signal, a terminal of the first integrated deviceor a terminal of the second integrated device to a site of an integratedcell disposed at a location of an integrated circuit. ii. The method ofclaim 10, wherein the first direction of orientation is orthogonal tothe second direction of orientation.
 12. The method of claim 10, whereinat least one of the first integrated device or the second integrateddevice comprises a thin gate oxide MOS transistor.
 13. The method ofclaim 10, wherein detecting, by the controller, the usability of thefirst integrated device and the second integrated device based on theelectrical characteristic indicative of the first direction oforientation or the second direction of orientation comprises: detectingwhich one of two integrated test devices exhibits a higher electricalcharacteristic, a first one of the two integrated test devices beingoriented in the first direction of orientation, a second one of the twointegrated test devices being oriented in the second direction oforientation, the electrical characteristic being different in each ofthe first direction of orientation and the second direction oforientation.
 14. The method of claim 13, wherein the electricalcharacteristic comprises a threshold voltage.
 15. The method of claim13, wherein the electrical characteristic comprises a leakage current.16. An integrated circuit, comprising: a first integrated device beingoperable in a first direction of orientation and exhibiting degradedoperation in a second direction of orientation compared to the firstdirection of orientation; a second integrated device being operable inthe second direction of orientation and exhibiting degraded operation inthe first direction of orientation compared to the second direction oforientation; a multiplexer having input terminals coupled to the firstintegrated device and the second integrated device, the multiplexerbeing configured to couple, based on a control signal, the firstintegrated device or the second integrated device to a site of anintegrated cell disposed at a location of the integrated circuit; and acontroller configured to determine an operability of the firstintegrated device and the second integrated device and generate thecontrol signal based on the operability of the first integrated deviceand the second integrated device.
 17. The integrated circuit of claim16, wherein the controller comprises: two integrated test devices,separate from the first integrated device and the second integrateddevice, respectively oriented in the first direction of orientation andthe second direction of orientation, each integrated test devicecomprising an element exhibiting a characteristic according to adirection of orientation and representative of a usable or non-usablecharacter of the first and second integrated devices; and a comparatorhaving a first input terminal coupled to a terminal of a first one ofthe two integrated test devices and a second input terminal coupled to aterminal of a second one of the two integrated test devices, thecomparator configured to compare voltages at the first input terminaland the second input terminal and generate the control signal based on acomparison of the voltages.
 18. The integrated circuit of claim 17,wherein each of the two integrated test devices comprises a thick gateoxide transistor, a longitudinal direction of each gate defining adirection of orientation of the thick gate oxide transistor.
 19. Theintegrated circuit of claim 16, wherein the first direction oforientation is substantially perpendicular to the second direction oforientation.
 20. The integrated circuit of claim 16, wherein each of thefirst integrated device and the second integrated device comprises athin gate oxide transistor having an oxide thickness less than or equalto about 2 nanometers.